Aptitude tricks

Shortcut methods/tricks in
*Percentage concept:

Important Points to Note:
 1.When any value increases by
 1.10%, it becomes 1.1 times of itself. (since 100+10 = 110% = 1.1)
 2.20%, it becomes 1.2 times of itself.
 3.36%, it becomes 1.36 times of itself.
 4.4%, it becomes 1.04 times of itself.

Thus we can see the effects on the values due to various percentage increases.
 2.When any value decreases by
 1.10%, it becomes 0.9 times of itself. (Since 100-10 = 90% = 0.9)
 2.20%, it becomes 0.8 times of itself
 3.36%, it becomes 0.64 times of itself
 4.4%, it becomes 0.96 times of itself.

Thus we can see the effects on a value due to various percentage decreases.

Note:

1. When a value is multiplied by a decimal more than 1 it will be increased and when multiplied by less than 1 it will be decreased.

2. The percentage increase or decrease depends on the decimal multiplied.

Eg: 0.7 => 30% decrease, 0.67 => 33% decrease, 0. 956 => 4.4% decrease and so on.

*Time and Distance problems:

1.Average Speed=Total distance/Total time

When they are more than one average speed then in order to find the average speeds of all here are some conditions
 1.When time is constant Average speed is Average of all speeds.
 2.When distance is constant then average speed is Harmonic mean of all average speeds.

For e.g: Two speeds s1,s2 Average speed=2/((1/s1)+(1/s2))

*Train Problems:

A train of length ‘l’ speed ‘s’ crossing a pole(man) of negligible length then time taken by train to train is

T=l/s

  A train of length ‘l’ and speed ‘s’ crossing a platform of length ‘lp’, then time taken by train to cross platform is
                                                                  T=(l+lp)/s

Relative speed Problems:

            In solving Relative speed problems there arises two cases

Case 1: When two objects of speeds s1, s2 are moving in the same direction then relative speed is difference of their speeds (i.e., s1~s2)

Case 2: When two objects of speeds s1, s2 are moving in the opposite direction then relative speed is sum of their speeds (i.e., s1+s2)

ARM architecture

ARM ARCHITECTURE
         The ARM architecture describes a family of RISC-based computer processors designed and licensed by British company ARM Holdings. It was first developed in the 1980s and globally as of 2013 is the most widely used 32-bit instruction set architecture in terms of quantity produced. In 2011 alone, producers of chips based on ARM architectures reported shipments of 7.9 billion ARM-based processors, representing 95% of smartphones, 90% of hard disk drives, 40% of digital televisions and set-top boxes, 15% of microcontrollers and 20% of mobile computers.
As an IP core business, ARM Holdings itself does not manufacture its own electronic chips, but licenses its designs to other semiconductor manufacturers. ARM-based processors and systems on a chip include the Qualcomm Snapdragon, nVidia Tegra, and Texas Instruments OMAP, as well as ARM's Cortex series and Apple System on Chips (used in its iPhones). The name was originally an acronym for Advanced RISC Machine, and in its early days Acorn RISC Machine.
Using a RISC based approach to computer design, ARM processors require significantly fewer transistors than processors that would typically be found in a traditional computer. The benefits of this approach are lower costs, less heat, and less power usage, traits that are desirable for use in light, portable, battery-powered devices such as smart phones and tablet computers. The reduced complexity and simpler design allows companies to build a low-energy system on a chip for an embedded system incorporating memory, interfaces, radios, etc. The earliest example was the Apple Newton tablet but this same approach is still used in the Apple A4 and A5 chips in the iPad.
ARM periodically releases updates to its core – currently ARMv7 and ARMv8 – which chip manufacturers can then license and use for their own devices. Variants are available for each of these to include or exclude optional capabilities. Current versions use 32-bit instructions with 32-bit addressed 1 byte wide memory which is effectively reduced to just over 24 bit addressing due to 4 byte alignment, with some addressing reserved in bytewise allocation for Memory Mapped I/O, but accommodates 16-bit instructions for economy and can also handle Java bytecodes which use 32-bit addresses. More recently, ARM architecture has included 64-bit versions – in 2012, Microsoft produced its new Surface tablet with ARM technology and AMD announced that it would start producing server chips based on the 64-bit ARM core in 2014.




The ARM architecture specifies the following CPU modes. At any moment in time, the CPU can be in only one mode, but it can switch modes due to external events (interrupts) or programmatically.
User mode
The only non-privileged mode.
System mode
The only privileged mode that is not entered by an exception. It can only be entered by executing an instruction that explicitly writes to the mode bits of the CPSR.
Supervisor (svc) mode
A privileged mode entered whenever the CPU is reset or when a SWI instruction is executed.
Abort mode
A privileged mode that is entered whenever a prefetch abort or data abort exception occurs.
Undefined mode
A privileged mode that is entered whenever an undefined instruction exception occurs.
Interrupt mode
A privileged mode that is entered whenever the processor accepts an IRQ interrupt.
Fast Interrupt mode
A privileged mode that is entered whenever the processor accepts an FIQ interrupt.
Hyp mode
A hypervisor mode introduced in armv-7a for cortex-A15 processor for providing hardware virtualization support.

ARM features and applications

FEATURES OF  ARM :               ARM is a RISC based computer processor.Using a RISC based approach to computer design, ARM processors require significantly fewer transistors than processors that would typically be found in a traditional computer. The benefits of this approach are lower costs, less heat, and less power usage, traits that are desirable for use in light, portable, battery-powered devices such as smart phones and tablet computers.The reduced complexity and simpler design allows companies to build a low-energy system on a chip for an embedded system incorporating memory, interfaces, radios, etc.
                          By 2005,  about 98% of the more than one billion mobile phones sold each year used at least one ARM processor. As of 2009, ARM processors accounted for approximately 90% of all embedded 32-bit RISC processors and were used extensively in consumer electronics, including personal digital assistants (PDAs), tablets, mobile phones, digital media and music players, hand-held game consoles, calculators and computer peripherals such as hard drives and routers.
   ARM CORES: 
    There are many extensions or updates of arm processor cores are introduced , some of them are tabulated as below,
    

Aerchitcture	Family
ARMv1	ARM1
ARMv2	ARM2, ARM3
ARMv3	ARM6, ARM7
ARMv4	StrongARM, ARM7TDMI, ARM9TDMI
ARMv5	ARM7EJ, ARM9E, ARM10E, XScale
ARMv6	ARM11
ARMv6-M	ARM Cortex-M0, ARM Cortex-M0+, ARM Cortex-M1
ARMv7	ARM Cortex-A5, ARM Cortex-A7, ARM Cortex-A8, ARM Cortex-A9, ARM Cortex-A15, ARM Cortex-R4, ARM Cortex-R5, ARM Cortex-R7
ARMv7-M	ARM Cortex-M3, ARM Cortex-M4
ARMv8-A	ARM Cortex-A53, ARM Cortex-A57

 APPLICATION OF ARM CORES:

            ARM cores are used in a number of products, particularly PDAs and smartphones. Some computing examples are the Microsoft Surface, Apple iPad and ASUS Eee Pad Transformer. Others include the Apple iPhone smartphone, iPod portable media player, Canon PowerShot A470 digital camera, Nintendo DS handheld game console and TomTomturn-by-turn navigation system.

  They also used it in developing Manchester University's computer ,SpiNNAKER, which uses arm core to simulate human brain.

    ARM chips are also used in Raspberry Pi, BeagleBoard, BeagleBone, PandaBoard, and other Single-board computers, because they are very small, inexpensive and consume very little power.

MIPS:

            It is acronym of  Microprocessor without Interlocked Pipeline Stages.

        It is RISC instruction set architecture developed by MIPS Technologies.Multiple revisions of the MIPS instruction set exist, including MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPS32, and MIPS64. The current revisions are MIPS32 (for 32-bit implementations) and MIPS64 (for 64-bit implementations).MIPS32 and MIPS64 define a control register set as well as the instruction set.

    MIPS implementations are primarily used in embedded systems such as Windows CE devices, routers, residential gateways, and video game consoles such as the Sony PlayStation 2 and PlayStation Portable. Until late 2006, they were also used in many of SGI's computer products. MIPS implementations were also used by Digital Equipment Corporation, NEC, Pyramid Technology, Siemens Nixdorf, Tandem Computers and others during the late 1980s and 1990s.

        One of the more interesting applications of the MIPS architecture is its use in massive processor count supercomputers.

MIPS

Designer	MIPS Technologies, Inc.
Bits	64-bit (32→64)
Introduced	1981
Design	RISC
Type	Register-Register
Encoding	Fixed
Branching	Condition register
Endianness	Bi
Extensions	MDMX, MIPS-3D

Software development Life Cycle

SDLC

The systems development life cycle (SDLC), or software development process in systems engineering, information systems and software engineering, is a process of creating or altering information systems, and the models and methodologies that people use to develop these systems software engineering, the SDLC concept underpins many kinds of software development methodologies. These methodologies form the framework for planning and controlling the creation of an information system.


The Systems development life cycle (SDLC) is a process used by a systems analyst to develop an information system, training, and user (stakeholder) ownership. The SDLC aims to produce a high quality system that meets or exceeds customer expectations, reaches completion within time and cost estimates, works effectively and efficiently in the current and planned Information Technology infrastructure, and is inexpensive to maintain and cost-effective to enhance.
Computer systems are complex and often (especially with the recent rise of service-oriented architecture) link multiple traditional systems potentially supplied by different software vendors. To manage this level of complexity, a number of SDLC models or methodologies have been created, such as "waterfall"; "spiral"; "Agile software development"; "rapid prototyping"; "incremental"; and "synchronize and stabilize".


                                              

Waterfall-model

The waterfall model is a sequential design process, often used in software development processes, in which progress is seen as flowing steadily downwards (like a waterfall) through the phases of Conception, Initiation, Analysis, Design, Construction, Testing, Production/Implementation, and Maintenance.
The waterfall development model originates in the manufacturing and construction industries; highly structured physical environments in which after-the-fact changes are prohibitively costly, if not impossible. Since no formal software development methodologies existed at the time, this hardware-oriented model was simply adapted for software development.[1]
The first known presentation describing use of similar phases in software engineering was held by Herbert D. Benington at Symposium on advanced programming methods for digital computers on 29 June 1956.[2] This presentation was about the development of software for SAGE. In 1983 the paper was republished[3] with a foreword by Benington pointing out that the process was not in fact performed in a strict top-down fashion, but depended on a prototype.


                                                 

V-model

The V-model represents a software development process (also applicable to hardware development) which may be considered an extension of the waterfall model. Instead of moving down in a linear way, the process steps are bent upwards after the coding phase, to form the typical V shape. The V-Model demonstrates the relationships between each phase of the development life cycle and its associated phase of testing. The horizontal and vertical axes represents time or project completeness (left-to-right) and level of abstraction (coarsest-grain abstraction uppermost), respectively.

                                                          

CMMI [capability Maturity Model Integration]

Capability Maturity Model Integration (CMMI) 

Is a process improvment approach. CMMI can be used to guide process improvement across a project, a division, or an entire organization. Processes are rated according to their maturity levels, which are defined as: Initial, Repeatable, Defined, Quantitatively Managed, Optimizing.

CMMI currently addresses three areas of interest:

1).Product and service development — CMMI for Development (CMMI-DEV),
2)Service establishment, management, — CMMI for Services (CMMI-SVC), and
3)Product and service acquisition — CMMI for Acquisition (CMMI-ACQ).

The different CMMI levels are:
1)Initial- processes unpredictable, poorly controlled and reactive.
2)Managed- processes characterized for projects and is often reactive.
3)Defined- processes characterized for the organisation and is proactive.
4)Quantitatively managed- processes measured and controlled.
5)Optimizing- focus on    process improvement.